Power consumption is becoming an increasingly important design consideration for electronic devices. Estimating power consumption for a circuit design that is to be implemented in a programmable IC (integrated circuit) such as a PLD (programmable logic device) is typically performed using designer-estimated resource counts or information from a completely implemented design. The power estimation also uses clock frequencies and global toggle rate defaults, which may be individually changed by the designer.
High levels of integration of circuit designs have presented challenges for estimating power consumption. Many circuit designs that were in the past implemented on multiple ICs (e.g., micro-processor, memory, SERDES interface, DSP, glue logic etc.) may now be implemented on a single chip. Multi-chip implementations permitted estimation of power consumption by summing the levels of power consumption of individual ICs numbers and estimated levels for the board level traces and passive components. The power consumption of each IC could be independently determined, estimated or obtained from the manufacturer. When components were added, removed, or changed during development of a design, a new estimate of power consumption could be easily determined with straightforward computations.
With a highly integrated design, estimating a level of power consumption is typically performed at the full-chip level using either resource-based or netlist-based power estimation tools. An example implementation of a highly integrated design is a circuit implemented on a chip or package that includes one or more processors, memory and field programmable gate array (FPGA) logic. Some tools that estimate the level of power consumption for such system on a chip (SOC) designs analyze the resource usage based on express resource counts or resource counts derived from the netlist in order to arrive at the estimated level of power consumption for the full SOC. This approach may be less accurate than is possible given additional information that may be available.
Some logic modules to be implemented in programmable logic may come from a source other than the party making the SOC design. The providers of those modules may have measured power consumption of those modules as implemented in an actual circuit. The measured level of power consumption is more accurate than an estimation based on the netlist or resource utilization. However, with tools that base power estimation on the resource count or netlist of the SOC design, the more accurate measured level of power consumption is not used in the estimation. Thus, the estimated level of power consumption may be less accurate than desirable.